library verilog;
use verilog.vl_types.all;
entity teste is
    port(
        clk_tst         : in     vl_logic;
        s_model         : in     vl_logic_vector(9 downto 0);
        s_refe          : in     vl_logic_vector(9 downto 0);
        finish          : in     vl_logic;
        fim             : out    vl_logic
    );
end teste;
